ARM Ltd.
DS_CM3
2024.06.02
ARM 32-bit Cortex-M3 based device
CM3
r2p1
little
3
false
8
32
DUALTIMER
Dual Timer
TIMER
0x0
0x0
0x3C
registers
n
DUALTIMER
Dual Timer interrupt
10
TIMER1BGLOAD
Timer 1 Background Load Register
0x18
read-write
n
0x0
0x0
TIMER1CONTROL
Timer 1 Control Register
0x8
read-write
n
0x0
0x0
InterruptEnable
Interrupt Enable bit
5
6
Disable
Interrupt is disabled.
0
Enable
Interrupt is enabled.
1
OneShotCount
Selects one-shot or wrapping counter mode.
0
1
Wrapping
Wrapping counter mode
0
OneShot
One-shot counter mode
1
TimerEnable
Timer Enable Enable bit.
7
8
Disable
Timer is disabled.
0
Enable
Timer is enabled.
1
TimerMode
Timer Mode bit
6
7
Free-Running
Free-Running timer mode.
0
Periodic
Periodic timer mode.
1
TimerPre
Timer prescale bits
2
4
divided by 1
clock is divided by 1
0
divided by 16
clock is divided by 16
1
divided by 256
clock is divided by 256
2
TimerSize
Selects 16-bit or 32- bit counter operation.
1
2
16-bit
16-bit counter mode
0
32-bit
32-bit counter mode
1
TIMER1INTCLR
Timer 1 Interrupt Clear Register
0xC
write-only
n
0x0
0x0
oneToClear
INT
interrupt
0
1
TIMER1LOAD
Timer 1 Load Register
0x0
read-write
n
0x0
0x0
TIMER1MIS
Timer 1 Mask Interrupt Status Register
0x14
read-only
n
0x0
0x0
MIS
Masked Timer interrupt
0
1
TIMER1RIS
Timer 1 Raw Interrupt Status Register
0x10
read-only
n
0x0
0x0
RIS
Raw Timer interrupt
0
1
TIMER1VALUE
Timer 1 Value Register
0x4
read-only
n
0x0
0x0
TIMER2BGLOAD
Timer 2 Background Load Register
0x38
read-write
n
0x0
0x0
TIMER2CONTROL
Timer 2 Control Register
0x28
read-write
n
0x0
0x0
InterruptEnable
Interrupt Enable bit.
5
6
Disable
Interrupt is disabled.
0
Enable
Interrupt is enabled.
1
OneShotCount
Selects one-shot or wrapping counter mode.
0
1
Wrapping
Wrapping counter mode
0
OneShot
One-shot counter mode
1
TimerEnable
Timer Enable Enable bit.
7
1
Disable
Timer is disabled.
0
Enable
Timer is enabled.
1
TimerMode
Timer Mode bit.
6
7
Free-Running
Free-Running timer mode.
0
Periodic
Periodic timer mode.
1
TimerPre
Timer prescale bits.
2
4
divided by 1
clock is divided by 1
0
divided by 16
clock is divided by 16
1
divided by 256
clock is divided by 256
2
TimerSize
Selects 16-bit or 32- bit counter operation.
1
2
16-bit
16-bit counter mode
0
32-bit
32-bit counter mode
1
TIMER2INTCLR
Timer 2 Interrupt Clear Register
0x2C
write-only
n
0x0
0x0
oneToClear
INT
interrupt
0
1
oneToClear
TIMER2LOAD
Timer 2 Load Register
0x20
read-write
n
0x0
0x0
TIMER2MIS
Timer 2 Mask Interrupt Status Register
0x34
read-only
n
0x0
0x0
MIS
Masked Timer interrupt
0
1
TIMER2RIS
Timer 2 Raw Interrupt Status Register
0x30
read-only
n
0x0
0x0
RIS
Raw Timer interrupt
0
1
TIMER2VALUE
Timer 2 Value Register
0x24
read-only
n
0x0
0x0
FPGASYS
FPGA System Control I/O
FPGASYS
0x0
0x0
0x50
registers
n
BUTTON
Button Connections
0x8
read-write
n
0x0
0x0
BUTTON0
0
1
Off
BUTTON is off
0
On
BUTTON is on
1
BUTTON1
1
2
Off
BUTTON is off
0
On
BUTTON is on
1
CLK100HZ
100Hz Up Counter
0x14
read-only
n
0x0
0x0
CLK1HZ
1Hz Up Counter
0x10
read-only
n
0x0
0x0
COUNTER
Cycle up counter
0x18
read-write
n
0x0
0x0
LED
LED Connections
0x0
read-write
n
0x0
0x0
LED0
0
1
Off
LED is off
0
On
LED is on
1
LED1
1
2
Off
LED is off
0
On
LED is on
1
MISC
Misc. Control
0x4C
read-write
n
0x0
0x0
ADC_SPI_nCS
7
8
CLCD_BL_CTRL
6
7
CLCD_CS
0
1
CLCD_RD
5
6
CLCD_RESET
3
4
CLCD_RS
4
5
SHIELD0_SPI_nCS
8
9
SHIELD1_SPI_nCS
9
10
SPI_nSS
1
2
PRESCALER
Reload value for prescaler counter
0x1C
read-write
n
0x0
0x0
PSCNTR
Prescale Counter
0x20
read-write
n
0x0
0x0
GPIO0
general-purpose I/O
GPIO
0x0
0x0
0x3C
registers
n
GPIO0
GPIO 0 combined interrupt
6
GPIO0_0
GPIO 0 Pin 0 interrupt
16
GPIO0_1
GPIO 0 Pin 1 interrupt
17
GPIO0_2
GPIO 0 Pin 2 interrupt
18
GPIO0_3
GPIO 0 Pin 3 interrupt
19
GPIO0_4
GPIO 0 Pin 4 interrupt
20
GPIO0_5
GPIO 0 Pin 5 interrupt
21
GPIO0_6
GPIO 0 Pin 6 interrupt
22
GPIO0_7
GPIO 0 Pin 7 interrupt
23
GPIO0_8
GPIO 0 Pin 8 interrupt
24
GPIO0_9
GPIO 0 Pin 9 interrupt
25
GPIO0_10
GPIO 0 Pin 10 interrupt
26
GPIO0_11
GPIO 0 Pin 11 interrupt
27
GPIO0_12
GPIO 0 Pin 12 interrupt
28
GPIO0_13
GPIO 0 Pin 13 interrupt
29
GPIO0_14
GPIO 0 Pin 14 interrupt
30
GPIO0_15
GPIO 0 Pin 15 interrupt
31
ALTFUNCCLR
Alternate function clear Register
0x1C
read-write
n
0x0
0x0
ALTFUNCSET
Alternate function set Register
0x18
read-write
n
0x0
0x0
DATA
Data Register
0x0
read-write
n
0x0
0x0
DATAOUT
Data Output Register
0x4
read-write
n
0x0
0x0
INTCLEAR
Interrupt CLEAR Register
INTSTATUS
0x38
write-only
n
0x0
0x0
oneToClear
INTENCLR
Interrupt enable clear Register
0x24
read-write
n
0x0
0x0
INTENSET
Interrupt enable set Register
0x20
read-write
n
0x0
0x0
INTPOLCLR
Polarity-level, edge interrupt configuration clear Register
0x34
read-write
n
0x0
0x0
INTPOLSET
Polarity-level, edge interrupt configuration set Register
0x30
read-write
n
0x0
0x0
INTSTATUS
Interrupt Status Register
0x38
read-only
n
0x0
0x0
INTTYPECLR
Interrupt type clear Register
0x2C
read-write
n
0x0
0x0
INTTYPESET
Interrupt type set Register
0x28
read-write
n
0x0
0x0
OUTENCLR
Ouptut enable clear Register
0x14
read-write
n
0x0
0x0
OUTENSET
Ouptut enable set Register
0x10
read-write
n
0x0
0x0
GPIO1
general-purpose I/O
GPIO
0x0
0x0
0x3C
registers
n
GPIO1
GPIO 1 combined interrupt
7
ALTFUNCCLR
Alternate function clear Register
0x1C
read-write
n
0x0
0x0
ALTFUNCSET
Alternate function set Register
0x18
read-write
n
0x0
0x0
DATA
Data Register
0x0
read-write
n
0x0
0x0
DATAOUT
Data Output Register
0x4
read-write
n
0x0
0x0
INTCLEAR
Interrupt CLEAR Register
INTSTATUS
0x38
write-only
n
0x0
0x0
oneToClear
INTENCLR
Interrupt enable clear Register
0x24
read-write
n
0x0
0x0
INTENSET
Interrupt enable set Register
0x20
read-write
n
0x0
0x0
INTPOLCLR
Polarity-level, edge interrupt configuration clear Register
0x34
read-write
n
0x0
0x0
INTPOLSET
Polarity-level, edge interrupt configuration set Register
0x30
read-write
n
0x0
0x0
INTSTATUS
Interrupt Status Register
0x38
read-only
n
0x0
0x0
INTTYPECLR
Interrupt type clear Register
0x2C
read-write
n
0x0
0x0
INTTYPESET
Interrupt type set Register
0x28
read-write
n
0x0
0x0
OUTENCLR
Ouptut enable clear Register
0x14
read-write
n
0x0
0x0
OUTENSET
Ouptut enable set Register
0x10
read-write
n
0x0
0x0
GPIO2
general-purpose I/O
GPIO
0x0
0x0
0x3C
registers
n
GPIO2
GPIO 2 combined interrupt
42
ALTFUNCCLR
Alternate function clear Register
0x1C
read-write
n
0x0
0x0
ALTFUNCSET
Alternate function set Register
0x18
read-write
n
0x0
0x0
DATA
Data Register
0x0
read-write
n
0x0
0x0
DATAOUT
Data Output Register
0x4
read-write
n
0x0
0x0
INTCLEAR
Interrupt CLEAR Register
INTSTATUS
0x38
write-only
n
0x0
0x0
oneToClear
INTENCLR
Interrupt enable clear Register
0x24
read-write
n
0x0
0x0
INTENSET
Interrupt enable set Register
0x20
read-write
n
0x0
0x0
INTPOLCLR
Polarity-level, edge interrupt configuration clear Register
0x34
read-write
n
0x0
0x0
INTPOLSET
Polarity-level, edge interrupt configuration set Register
0x30
read-write
n
0x0
0x0
INTSTATUS
Interrupt Status Register
0x38
read-only
n
0x0
0x0
INTTYPECLR
Interrupt type clear Register
0x2C
read-write
n
0x0
0x0
INTTYPESET
Interrupt type set Register
0x28
read-write
n
0x0
0x0
OUTENCLR
Ouptut enable clear Register
0x14
read-write
n
0x0
0x0
OUTENSET
Ouptut enable set Register
0x10
read-write
n
0x0
0x0
GPIO3
general-purpose I/O
GPIO
0x0
0x0
0x3C
registers
n
GPIO3
GPIO 3 combined interrupt
43
ALTFUNCCLR
Alternate function clear Register
0x1C
read-write
n
0x0
0x0
ALTFUNCSET
Alternate function set Register
0x18
read-write
n
0x0
0x0
DATA
Data Register
0x0
read-write
n
0x0
0x0
DATAOUT
Data Output Register
0x4
read-write
n
0x0
0x0
INTCLEAR
Interrupt CLEAR Register
INTSTATUS
0x38
write-only
n
0x0
0x0
oneToClear
INTENCLR
Interrupt enable clear Register
0x24
read-write
n
0x0
0x0
INTENSET
Interrupt enable set Register
0x20
read-write
n
0x0
0x0
INTPOLCLR
Polarity-level, edge interrupt configuration clear Register
0x34
read-write
n
0x0
0x0
INTPOLSET
Polarity-level, edge interrupt configuration set Register
0x30
read-write
n
0x0
0x0
INTSTATUS
Interrupt Status Register
0x38
read-only
n
0x0
0x0
INTTYPECLR
Interrupt type clear Register
0x2C
read-write
n
0x0
0x0
INTTYPESET
Interrupt type set Register
0x28
read-write
n
0x0
0x0
OUTENCLR
Ouptut enable clear Register
0x14
read-write
n
0x0
0x0
OUTENSET
Ouptut enable set Register
0x10
read-write
n
0x0
0x0
GPIO4
general-purpose I/O
GPIO
0x0
0x0
0x3C
registers
n
GPIO4
GPIO 4 combined interrupt
54
ALTFUNCCLR
Alternate function clear Register
0x1C
read-write
n
0x0
0x0
ALTFUNCSET
Alternate function set Register
0x18
read-write
n
0x0
0x0
DATA
Data Register
0x0
read-write
n
0x0
0x0
DATAOUT
Data Output Register
0x4
read-write
n
0x0
0x0
INTCLEAR
Interrupt CLEAR Register
INTSTATUS
0x38
write-only
n
0x0
0x0
oneToClear
INTENCLR
Interrupt enable clear Register
0x24
read-write
n
0x0
0x0
INTENSET
Interrupt enable set Register
0x20
read-write
n
0x0
0x0
INTPOLCLR
Polarity-level, edge interrupt configuration clear Register
0x34
read-write
n
0x0
0x0
INTPOLSET
Polarity-level, edge interrupt configuration set Register
0x30
read-write
n
0x0
0x0
INTSTATUS
Interrupt Status Register
0x38
read-only
n
0x0
0x0
INTTYPECLR
Interrupt type clear Register
0x2C
read-write
n
0x0
0x0
INTTYPESET
Interrupt type set Register
0x28
read-write
n
0x0
0x0
OUTENCLR
Ouptut enable clear Register
0x14
read-write
n
0x0
0x0
OUTENSET
Ouptut enable set Register
0x10
read-write
n
0x0
0x0
GPIO5
general-purpose I/O
GPIO
0x0
0x0
0x3C
registers
n
GPIO5
GPIO 5 combined interrupt
55
ALTFUNCCLR
Alternate function clear Register
0x1C
read-write
n
0x0
0x0
ALTFUNCSET
Alternate function set Register
0x18
read-write
n
0x0
0x0
DATA
Data Register
0x0
read-write
n
0x0
0x0
DATAOUT
Data Output Register
0x4
read-write
n
0x0
0x0
INTCLEAR
Interrupt CLEAR Register
INTSTATUS
0x38
write-only
n
0x0
0x0
oneToClear
INTENCLR
Interrupt enable clear Register
0x24
read-write
n
0x0
0x0
INTENSET
Interrupt enable set Register
0x20
read-write
n
0x0
0x0
INTPOLCLR
Polarity-level, edge interrupt configuration clear Register
0x34
read-write
n
0x0
0x0
INTPOLSET
Polarity-level, edge interrupt configuration set Register
0x30
read-write
n
0x0
0x0
INTSTATUS
Interrupt Status Register
0x38
read-only
n
0x0
0x0
INTTYPECLR
Interrupt type clear Register
0x2C
read-write
n
0x0
0x0
INTTYPESET
Interrupt type set Register
0x28
read-write
n
0x0
0x0
OUTENCLR
Ouptut enable clear Register
0x14
read-write
n
0x0
0x0
OUTENSET
Ouptut enable set Register
0x10
read-write
n
0x0
0x0
I2CAUDIO
Simple I2C peripheral
I2C
0x0
0x0
0x8
registers
n
CONTROL
Control Status
0x0
read-only
n
0x0
0x0
SCL
Serial clock line
0
1
SDA
Serial data line
1
2
CONTROLC
Control Clear
0x4
write-only
n
0x0
0x0
SCL
Serial clock line
0
1
SDA
Serial data line
1
2
CONTROLS
Control Set
CONTROL
0x0
write-only
n
0x0
0x0
SCL
Serial clock line
0
1
SDA
Serial data line
1
2
I2CCLCD
Simple I2C peripheral
I2C
0x0
0x0
0x8
registers
n
CONTROL
Control Status
0x0
read-only
n
0x0
0x0
SCL
Serial clock line
0
1
SDA
Serial data line
1
2
CONTROLC
Control Clear
0x4
write-only
n
0x0
0x0
SCL
Serial clock line
0
1
SDA
Serial data line
1
2
CONTROLS
Control Set
CONTROL
0x0
write-only
n
0x0
0x0
SCL
Serial clock line
0
1
SDA
Serial data line
1
2
I2CSH0
Simple I2C peripheral
I2C
0x0
0x0
0x8
registers
n
CONTROL
Control Status
0x0
read-only
n
0x0
0x0
SCL
Serial clock line
0
1
SDA
Serial data line
1
2
CONTROLC
Control Clear
0x4
write-only
n
0x0
0x0
SCL
Serial clock line
0
1
SDA
Serial data line
1
2
CONTROLS
Control Set
CONTROL
0x0
write-only
n
0x0
0x0
SCL
Serial clock line
0
1
SDA
Serial data line
1
2
I2CSH1
Simple I2C peripheral
I2C
0x0
0x0
0x8
registers
n
CONTROL
Control Status
0x0
read-only
n
0x0
0x0
SCL
Serial clock line
0
1
SDA
Serial data line
1
2
CONTROLC
Control Clear
0x4
write-only
n
0x0
0x0
SCL
Serial clock line
0
1
SDA
Serial data line
1
2
CONTROLS
Control Set
CONTROL
0x0
write-only
n
0x0
0x0
SCL
Serial clock line
0
1
SDA
Serial data line
1
2
I2S
simple audio I2S peripheral
I2S
0x0
0x0
0x30C
registers
n
I2S
I2S interrupt
48
CONTROL
CONTROL Register
0x0
read-write
n
0x0
0x0
DIVIDE
Divide ratio Register
0xC
read-write
n
0x0
0x0
ERROR
Error Status Register
0x8
read-only
n
0x0
0x0
ERRORCLR
Error Clear Register
ERROR
0x8
write-only
n
0x0
0x0
ITCR
Integration Test Control Register
0x300
read-write
n
0x0
0x0
ITIP1
Integration Test Input Register 1
0x304
write-only
n
0x0
0x0
ITOP1
Integration Test Output Register 1
0x308
write-only
n
0x0
0x0
RXBUF
Receive Buffer
0x14
read-only
n
0x0
0x0
STATUS
STATUS Register
0x4
read-only
n
0x0
0x0
TXBUF
Transmit Buffer
0x10
write-only
n
0x0
0x0
RTC
Real Time Clock (PL031)
RTC
0x0
0x0
0x20
registers
n
RTC
RTC interrupt
5
CR
Control register
0xC
read-write
n
0x0
0x0
DR
Data register
0x0
read-only
n
0x0
0x0
ICR
Interrupt clear register
0x1C
write-only
n
0x0
0x0
oneToClear
IMSC
Interrupt mask set and clear register
0x10
read-write
n
0x0
0x0
LR
Load register
0x8
read-write
n
0x0
0x0
MIS
Masked interrupt status register
0x18
read-only
n
0x0
0x0
MR
Match register
0x4
read-write
n
0x0
0x0
RIS
Raw interrupt status register
0x14
read-only
n
0x0
0x0
SCC
Serial Communication Controller
SCC
0x0
0x0
0x1000
registers
n
AID
AID register
0xFF8
read-only
n
0x0
0x0
FPGA_BUILD
FPGA Build Number
24
32
MPS2_REV
V2M-MPS2 target Board Revision
20
24
A
Revision A
0
B
Revision B
1
C
Revision C
2
NUM_CFG_REG
Number of SCC configuration register
0
8
CFG_REG0
Configuration register 0
0x0
read-write
n
0x0
0x0
REMAP
REMAP Block RAM to ZBT
0
1
CFG_REG1
Configuration register 1
0x4
read-write
n
0x0
0x0
MCC_LED0
MCC LED 0
0
1
Off
LED is off
0
On
LED is on
1
MCC_LED1
MCC LED 1
1
2
Off
LED is off
0
On
LED is on
1
MCC_LED2
MCC LED 2
2
3
Off
LED is off
0
On
LED is on
1
MCC_LED3
MCC LED 3
3
4
Off
LED is off
0
On
LED is on
1
MCC_LED4
MCC LED 4
4
5
Off
LED is off
0
On
LED is on
1
MCC_LED5
MCC LED 5
5
6
Off
LED is off
0
On
LED is on
1
MCC_LED6
MCC LED 6
6
7
Off
LED is off
0
On
LED is on
1
MCC_LED7
MCC LED 7
7
8
Off
LED is off
0
On
LED is on
1
CFG_REG2
Configuration register 2
0x8
read-only
n
0x0
0x0
CFG_REG3
Configuration register 3
0xC
read-only
n
0x0
0x0
MCC_SWITCH1
MCC switch 1
1
2
Off
Switch is off
0
On
Switch is on
1
MCC_SWITCH2
MCC switch 2
2
3
Off
Switch is off
0
On
Switch is on
1
MCC_SWITCH3
MCC switch 3
3
4
Off
Switch is off
0
On
Switch is on
1
MCC_SWITCH4
MCC switch 4
4
5
Off
Switch is off
0
On
Switch is on
1
MCC_SWITCH5
MCC switch 5
5
6
Off
Switch is off
0
On
Switch is on
1
MCC_SWITCH6
MCC switch 6
6
7
Off
Switch is off
0
On
Switch is on
1
MCC_SWITCH7
MCC switch 7
7
8
Off
Switch is off
0
On
Switch is on
1
MCC_SWITCHE0
MCC switch 0
0
1
Off
Switch is off
0
On
Switch is on
1
CFG_REG4
Configuration register 4
0x10
read-only
n
0x0
0x0
BRDREV
Board Revision
0
4
DLL
DLL Lock Register
0x100
read-write
n
0x0
0x0
LOCKED
Complete Flag
0
1
LOCKED_MASKED
Error Flag
24
32
LOCK_UNLOCK
Complete Flag
16
24
ID
AID register
0xFFC
read-only
n
0x0
0x0
APP_NOTE_VAR
Application note IP variant number
20
24
APP_REV
Application note IP revision number
0
4
IMPLEMENTER_ID
Implementer ID: 0x41 = ARM
24
32
ARM
ARM
0x41
IP_ARCH
IP Architecture
16
20
AHB
AHB
0x4
PRI_NUM
Primary Part Number: 383 = AN383
4
12
SYS_CFGCTRL
System configuration control register
0xA8
read-write
n
0x0
0x0
DEVICE
Device (value of 0/1/2 for supported clocks
0
12
RFUNCVAL
Function value
20
26
RW_ACCESS
Read/Write Access
30
31
START
Start: generates interrupt on write to this bit
31
32
SYS_CFGDATA_OUT
System configuration data register OUT
0xA4
read-write
n
0x0
0x0
SYS_CFGDATA_RTN
System configuration data register RTN
0xA0
read-write
n
0x0
0x0
SYS_CFGSTAT
System configuration status register
0xAC
read-write
n
0x0
0x0
COMPLETE
Complete Flag
0
1
ERROR
Error Flag
1
2
SPIADC
Synchronous Serial Port (PL022) extern
SPI
0x0
0x0
0x40
registers
n
MPS2_SPI2
SPI ADC interrupt
51
CPSR
Clock prescale register
0x10
read-write
n
0x0
0x0
CPSDVSR
Clock prescale divisor
0
8
CR0
Control register 0
0x0
read-write
n
0x0
0x0
DSS
Data Size Select
0
4
FRF
Frame format
4
6
SCR
Serial clock rate
8
16
SPH
SSPCLKOUT phase
7
8
SPO
SSPCLKOUT polarity
6
7
CR1
Control register 1
0x4
read-write
n
0x0
0x0
LBM
Loop back mode
0
1
MS
Master or slave mode select
2
3
SOD
Slave-mode output disable
3
4
SSE
Synchronous serial port enable
1
2
DMACR
DMA control register
0x24
read-write
n
0x0
0x0
RXDMAE
Receive DMA Enable
0
1
TXDMAE
Transmit DMA Enable
1
2
DR
Data register
0x8
read-write
n
0x0
0x0
Data
Transmit/Receive FIFO
0
16
ICR
Interrupt clear register
0x20
write-only
n
0x0
0x0
RORIC
Clears the SSPRORINTR interrupt
0
1
RTIC
Clears the SSPRTINTR interrupt
1
2
IMSC
Interrupt mask set or clear register
0x14
read-write
n
0x0
0x0
RORIM
Receive overrun interrupt mask
0
1
RTIM
Receive timeout interrupt mask
1
2
RXIM
Receive FIFO interrupt mask
2
3
TXIM
Transmit FIFO interrupt mask
3
4
MIS
Masked interrupt status register
0x1C
read-only
n
0x0
0x0
RORMIS
receive over run masked interrupt state
0
1
RTMIS
receive timeout masked interrupt state
1
2
RXMIS
receive FIFO masked interrupt state
2
3
TXMIS
transmit FIFO masked interrupt state
3
4
RIS
Raw interrupt status register
0x18
read-only
n
0x0
0x0
RORRIS
receive over run raw interrupt state
0
1
RTRIS
receive timeout raw interrupt state
1
2
RXRIS
receive FIFO raw interrupt state
2
3
TXRIS
transmit FIFOraw interrupt state
3
4
SR
Status register
0xC
read-only
n
0x0
0x0
BSY
PrimeCell SSP busy flag
4
5
RFF
Receive FIFO full
3
4
RNE
Receive FIFO not empty
2
3
TFE
Transmit FIFO empty
0
1
TNF
Transmit FIFO not full
1
2
SPICLCD
Synchronous Serial Port (PL022) extern
SPI
0x0
0x0
0x40
registers
n
MPS2_SPI1
SPI CLCD interrupt
50
CPSR
Clock prescale register
0x10
read-write
n
0x0
0x0
CPSDVSR
Clock prescale divisor
0
8
CR0
Control register 0
0x0
read-write
n
0x0
0x0
DSS
Data Size Select
0
4
FRF
Frame format
4
6
SCR
Serial clock rate
8
16
SPH
SSPCLKOUT phase
7
8
SPO
SSPCLKOUT polarity
6
7
CR1
Control register 1
0x4
read-write
n
0x0
0x0
LBM
Loop back mode
0
1
MS
Master or slave mode select
2
3
SOD
Slave-mode output disable
3
4
SSE
Synchronous serial port enable
1
2
DMACR
DMA control register
0x24
read-write
n
0x0
0x0
RXDMAE
Receive DMA Enable
0
1
TXDMAE
Transmit DMA Enable
1
2
DR
Data register
0x8
read-write
n
0x0
0x0
Data
Transmit/Receive FIFO
0
16
ICR
Interrupt clear register
0x20
write-only
n
0x0
0x0
RORIC
Clears the SSPRORINTR interrupt
0
1
RTIC
Clears the SSPRTINTR interrupt
1
2
IMSC
Interrupt mask set or clear register
0x14
read-write
n
0x0
0x0
RORIM
Receive overrun interrupt mask
0
1
RTIM
Receive timeout interrupt mask
1
2
RXIM
Receive FIFO interrupt mask
2
3
TXIM
Transmit FIFO interrupt mask
3
4
MIS
Masked interrupt status register
0x1C
read-only
n
0x0
0x0
RORMIS
receive over run masked interrupt state
0
1
RTMIS
receive timeout masked interrupt state
1
2
RXMIS
receive FIFO masked interrupt state
2
3
TXMIS
transmit FIFO masked interrupt state
3
4
RIS
Raw interrupt status register
0x18
read-only
n
0x0
0x0
RORRIS
receive over run raw interrupt state
0
1
RTRIS
receive timeout raw interrupt state
1
2
RXRIS
receive FIFO raw interrupt state
2
3
TXRIS
transmit FIFOraw interrupt state
3
4
SR
Status register
0xC
read-only
n
0x0
0x0
BSY
PrimeCell SSP busy flag
4
5
RFF
Receive FIFO full
3
4
RNE
Receive FIFO not empty
2
3
TFE
Transmit FIFO empty
0
1
TNF
Transmit FIFO not full
1
2
SPIEXT
Synchronous Serial Port (PL022) extern
SPI
0x0
0x0
0x40
registers
n
MPS2_SPI0
SPI Header interrupt
49
CPSR
Clock prescale register
0x10
read-write
n
0x0
0x0
CPSDVSR
Clock prescale divisor
0
8
CR0
Control register 0
0x0
read-write
n
0x0
0x0
DSS
Data Size Select
0
4
FRF
Frame format
4
6
SCR
Serial clock rate
8
16
SPH
SSPCLKOUT phase
7
8
SPO
SSPCLKOUT polarity
6
7
CR1
Control register 1
0x4
read-write
n
0x0
0x0
LBM
Loop back mode
0
1
MS
Master or slave mode select
2
3
SOD
Slave-mode output disable
3
4
SSE
Synchronous serial port enable
1
2
DMACR
DMA control register
0x24
read-write
n
0x0
0x0
RXDMAE
Receive DMA Enable
0
1
TXDMAE
Transmit DMA Enable
1
2
DR
Data register
0x8
read-write
n
0x0
0x0
Data
Transmit/Receive FIFO
0
16
ICR
Interrupt clear register
0x20
write-only
n
0x0
0x0
RORIC
Clears the SSPRORINTR interrupt
0
1
RTIC
Clears the SSPRTINTR interrupt
1
2
IMSC
Interrupt mask set or clear register
0x14
read-write
n
0x0
0x0
RORIM
Receive overrun interrupt mask
0
1
RTIM
Receive timeout interrupt mask
1
2
RXIM
Receive FIFO interrupt mask
2
3
TXIM
Transmit FIFO interrupt mask
3
4
MIS
Masked interrupt status register
0x1C
read-only
n
0x0
0x0
RORMIS
receive over run masked interrupt state
0
1
RTMIS
receive timeout masked interrupt state
1
2
RXMIS
receive FIFO masked interrupt state
2
3
TXMIS
transmit FIFO masked interrupt state
3
4
RIS
Raw interrupt status register
0x18
read-only
n
0x0
0x0
RORRIS
receive over run raw interrupt state
0
1
RTRIS
receive timeout raw interrupt state
1
2
RXRIS
receive FIFO raw interrupt state
2
3
TXRIS
transmit FIFOraw interrupt state
3
4
SR
Status register
0xC
read-only
n
0x0
0x0
BSY
PrimeCell SSP busy flag
4
5
RFF
Receive FIFO full
3
4
RNE
Receive FIFO not empty
2
3
TFE
Transmit FIFO empty
0
1
TNF
Transmit FIFO not full
1
2
SPISH0
Synchronous Serial Port (PL022) extern
SPI
0x0
0x0
0x40
registers
n
MPS2_SPI3
SPI Shield2 interrupt
52
CPSR
Clock prescale register
0x10
read-write
n
0x0
0x0
CPSDVSR
Clock prescale divisor
0
8
CR0
Control register 0
0x0
read-write
n
0x0
0x0
DSS
Data Size Select
0
4
FRF
Frame format
4
6
SCR
Serial clock rate
8
16
SPH
SSPCLKOUT phase
7
8
SPO
SSPCLKOUT polarity
6
7
CR1
Control register 1
0x4
read-write
n
0x0
0x0
LBM
Loop back mode
0
1
MS
Master or slave mode select
2
3
SOD
Slave-mode output disable
3
4
SSE
Synchronous serial port enable
1
2
DMACR
DMA control register
0x24
read-write
n
0x0
0x0
RXDMAE
Receive DMA Enable
0
1
TXDMAE
Transmit DMA Enable
1
2
DR
Data register
0x8
read-write
n
0x0
0x0
Data
Transmit/Receive FIFO
0
16
ICR
Interrupt clear register
0x20
write-only
n
0x0
0x0
RORIC
Clears the SSPRORINTR interrupt
0
1
RTIC
Clears the SSPRTINTR interrupt
1
2
IMSC
Interrupt mask set or clear register
0x14
read-write
n
0x0
0x0
RORIM
Receive overrun interrupt mask
0
1
RTIM
Receive timeout interrupt mask
1
2
RXIM
Receive FIFO interrupt mask
2
3
TXIM
Transmit FIFO interrupt mask
3
4
MIS
Masked interrupt status register
0x1C
read-only
n
0x0
0x0
RORMIS
receive over run masked interrupt state
0
1
RTMIS
receive timeout masked interrupt state
1
2
RXMIS
receive FIFO masked interrupt state
2
3
TXMIS
transmit FIFO masked interrupt state
3
4
RIS
Raw interrupt status register
0x18
read-only
n
0x0
0x0
RORRIS
receive over run raw interrupt state
0
1
RTRIS
receive timeout raw interrupt state
1
2
RXRIS
receive FIFO raw interrupt state
2
3
TXRIS
transmit FIFOraw interrupt state
3
4
SR
Status register
0xC
read-only
n
0x0
0x0
BSY
PrimeCell SSP busy flag
4
5
RFF
Receive FIFO full
3
4
RNE
Receive FIFO not empty
2
3
TFE
Transmit FIFO empty
0
1
TNF
Transmit FIFO not full
1
2
SPISH1
Synchronous Serial Port (PL022) extern
SPI
0x0
0x0
0x40
registers
n
MPS2_SPI4
SPI Shield1 interrupt
53
CPSR
Clock prescale register
0x10
read-write
n
0x0
0x0
CPSDVSR
Clock prescale divisor
0
8
CR0
Control register 0
0x0
read-write
n
0x0
0x0
DSS
Data Size Select
0
4
FRF
Frame format
4
6
SCR
Serial clock rate
8
16
SPH
SSPCLKOUT phase
7
8
SPO
SSPCLKOUT polarity
6
7
CR1
Control register 1
0x4
read-write
n
0x0
0x0
LBM
Loop back mode
0
1
MS
Master or slave mode select
2
3
SOD
Slave-mode output disable
3
4
SSE
Synchronous serial port enable
1
2
DMACR
DMA control register
0x24
read-write
n
0x0
0x0
RXDMAE
Receive DMA Enable
0
1
TXDMAE
Transmit DMA Enable
1
2
DR
Data register
0x8
read-write
n
0x0
0x0
Data
Transmit/Receive FIFO
0
16
ICR
Interrupt clear register
0x20
write-only
n
0x0
0x0
RORIC
Clears the SSPRORINTR interrupt
0
1
RTIC
Clears the SSPRTINTR interrupt
1
2
IMSC
Interrupt mask set or clear register
0x14
read-write
n
0x0
0x0
RORIM
Receive overrun interrupt mask
0
1
RTIM
Receive timeout interrupt mask
1
2
RXIM
Receive FIFO interrupt mask
2
3
TXIM
Transmit FIFO interrupt mask
3
4
MIS
Masked interrupt status register
0x1C
read-only
n
0x0
0x0
RORMIS
receive over run masked interrupt state
0
1
RTMIS
receive timeout masked interrupt state
1
2
RXMIS
receive FIFO masked interrupt state
2
3
TXMIS
transmit FIFO masked interrupt state
3
4
RIS
Raw interrupt status register
0x18
read-only
n
0x0
0x0
RORRIS
receive over run raw interrupt state
0
1
RTRIS
receive timeout raw interrupt state
1
2
RXRIS
receive FIFO raw interrupt state
2
3
TXRIS
transmit FIFOraw interrupt state
3
4
SR
Status register
0xC
read-only
n
0x0
0x0
BSY
PrimeCell SSP busy flag
4
5
RFF
Receive FIFO full
3
4
RNE
Receive FIFO not empty
2
3
TFE
Transmit FIFO empty
0
1
TNF
Transmit FIFO not full
1
2
SYSCTRL
System Control
SYSCTRL
0x0
0x0
0x14
registers
n
PMUCTRL
PMU Control Register
0x4
read-write
n
0x0
0x0
REMAP
Remap Control Register
0x0
read-write
n
0x0
0x0
RESETOP
Reset Option Register
0x8
read-write
n
0x0
0x0
RSTINFO
Reset Information Register
0x10
read-write
n
0x0
0x0
TIMER0
Timer 0
TIMER
0x0
0x0
0x10
registers
n
TIMER0
Timer 0 interrupt
8
CTRL
Control Register
0x0
read-write
n
0x0
0x0
ENABLE
Enable
0
1
Disable
Timer is disabled
0
Enable
Timer is enabled
1
EXTCLK
External Clock Enable
2
3
Disable
External Clock s disabled
0
Enable
External Clock is enabled
1
EXTIN
External Input as Enable
1
2
Disable
External Input as Enable is disabled
0
Enable
External Input as Enable is enabled
1
INTEN
Interrupt Enable
3
4
Disable
Interrupt is disabled
0
Enable
Interrupt is enabled
1
INTCLEAR
Timer Interrupt clear register
INTSTATUS
0xC
write-only
n
0x0
0x0
oneToClear
INTSTATUS
Timer Interrupt status register
0xC
read-only
n
0x0
0x0
RELOAD
Counter Reload Value
0x8
read-write
n
0x0
0x0
VALUE
Current Timer Counter Value
0x4
read-write
n
0x0
0x0
TIMER1
Timer 1
TIMER
0x0
0x0
0x10
registers
n
TIMER1
Timer 1 interrupt
9
CTRL
Control Register
0x0
read-write
n
0x0
0x0
ENABLE
Enable
0
1
Disable
Timer is disabled
0
Enable
Timer is enabled
1
EXTCLK
External Clock Enable
2
3
Disable
External Clock s disabled
0
Enable
External Clock is enabled
1
EXTIN
External Input as Enable
1
2
Disable
External Input as Enable is disabled
0
Enable
External Input as Enable is enabled
1
INTEN
Interrupt Enable
3
4
Disable
Interrupt is disabled
0
Enable
Interrupt is enabled
1
INTCLEAR
Timer Interrupt clear register
INTSTATUS
0xC
write-only
n
0x0
0x0
oneToClear
INTSTATUS
Timer Interrupt status register
0xC
read-only
n
0x0
0x0
RELOAD
Counter Reload Value
0x8
read-write
n
0x0
0x0
VALUE
Current Timer Counter Value
0x4
read-write
n
0x0
0x0
TRNG
True Random Number Generator
TRNG
0x0
0x0
0x1F0
registers
n
TRNG
True Random Generator interrupt
44
AUTOCORR_STATISTIC
Autocorrelation Statistic register
0x134
read-write
n
0x0
0x0
BUSY
TRNG Busy status register
0x1B8
read-only
n
0x0
0x0
CONFIG
TRNG Configuration Register
0x10C
read-write
n
0x0
0x0
DEBUG_CONTROL
TRNG Debug Control register
0x138
read-only
n
0x0
0x0
EHR_DATA0
EHR Data register
0x114
-1
read-only
n
0x0
0x0
EHR_DATA1
EHR Data register
0x118
-1
read-only
n
0x0
0x0
EHR_DATA2
EHR Data register
0x11C
-1
read-only
n
0x0
0x0
EHR_DATA3
EHR Data register
0x120
-1
read-only
n
0x0
0x0
EHR_DATA4
EHR Data register
0x124
-1
read-only
n
0x0
0x0
EHR_DATA5
EHR Data register
0x128
-1
read-only
n
0x0
0x0
EHR_DATA[0]
EHR Data register
0x228
read-only
n
0x0
0x0
EHR_DATA[1]
EHR Data register
0x340
read-only
n
0x0
0x0
EHR_DATA[2]
EHR Data register
0x45C
read-only
n
0x0
0x0
EHR_DATA[3]
EHR Data register
0x57C
read-only
n
0x0
0x0
EHR_DATA[4]
EHR Data register
0x6A0
read-only
n
0x0
0x0
EHR_DATA[5]
EHR Data register
0x7C8
read-only
n
0x0
0x0
ICR
Interrupt status bit Clear Register
0x108
write-only
n
0x0
0x0
ISR
Interrupt Status Register
0x104
read-only
n
0x0
0x0
RND_SOURCE_ENABLE
Random Source Enable registe
0x12C
read-write
n
0x0
0x0
RNG_IMR
Interrupt Masking Register
0x100
read-write
n
0x0
0x0
RST_BIST_COUNTER0
RNG BIST Counter register
0x1E0
-1
read-write
n
0x0
0x0
RST_BIST_COUNTER1
RNG BIST Counter register
0x1E4
-1
read-write
n
0x0
0x0
RST_BIST_COUNTER2
RNG BIST Counter register
0x1E8
-1
read-write
n
0x0
0x0
RST_BIST_COUNTER[0]
RNG BIST Counter register
0x3C0
read-write
n
0x0
0x0
RST_BIST_COUNTER[1]
RNG BIST Counter register
0x5A4
read-write
n
0x0
0x0
RST_BIST_COUNTER[2]
RNG BIST Counter register
0x78C
read-write
n
0x0
0x0
RST_BITS_COUNTER
Reset Bits Counter register
0x1BC
write-only
n
0x0
0x0
SAMPLE_CNT1
Sample Counter register
0x130
read-write
n
0x0
0x0
SW_RESET
TRNG Software Reset Register
0x140
write-only
n
0x0
0x0
VALID
TRNG Valid register
0x110
read-only
n
0x0
0x0
UART0
UART 0
UART
0x0
0x0
0x14
registers
n
UART0
UART 0 interrupt
0
UART_OVF
UART 0/1/2/3/4 overflow interrupt
12
BAUDDIV
Baudrate Divider
0x10
read-write
n
0x0
0x0
CTRL
UART Control Register
0x8
read-write
n
0x0
0x0
HSTX
High Speed Test Mode for TX only
6
7
Disable
Disabled
0
Enable
Enabled
1
RVOVINT
RX Overrun Interrupt Enable
5
6
Disable
Disabled
0
Enable
Enabled
1
RXEN
RX Enable
1
2
Disable
Disabled
0
Enable
Enabled
1
RXINT
RX Interrupt Enable
3
4
Disable
Disabled
0
Enable
Enabled
1
TXEN
TX Enable
0
1
Disable
Disabled
0
Enable
Enabled
1
TXINT
TX Interrupt Enable
2
3
Disable
Disabled
0
Enable
Enabled
1
TXOVINT
TX Overrun Interrupt Enable
4
5
Disable
Disabled
0
Enable
Enabled
1
DATA
Recieve and Transmit Data Value
0x0
read-write
n
0x0
0x0
INTCLEAR
UART Interrupt CLEAR Register
INTSTATUS
0xC
write-only
n
0x0
0x0
RXINT
RX interrupt
1
2
oneToClear
RXOV
RX Overrun interrupt
3
4
oneToClear
TXINT
TX interrupt
0
1
oneToClear
TXOV
TX Overrun interrupt
2
3
oneToClear
INTSTATUS
UART Interrupt Status Register
0xC
read-only
n
0x0
0x0
RXINT
RX interrupt
1
2
RXOV
RX Overrun interrupt
3
4
TXINT
TX interrupt
0
1
TXOV
TX Overrun interrupt
2
3
STATE
UART Status Register
0x4
read-write
n
0x0
0x0
RXBF
RX Buffer Full
1
2
read-only
RXOV
RX Buffer Overun (write 1 to clear)
3
4
oneToClear
TXBF
TX Buffer Full
0
1
read-only
TXOV
TX Buffer Overun (write 1 to clear)
2
3
oneToClear
UART1
UART 1
UART
0x0
0x0
0x14
registers
n
UART1
UART 1 interrupt
2
BAUDDIV
Baudrate Divider
0x10
read-write
n
0x0
0x0
CTRL
UART Control Register
0x8
read-write
n
0x0
0x0
HSTX
High Speed Test Mode for TX only
6
7
Disable
Disabled
0
Enable
Enabled
1
RVOVINT
RX Overrun Interrupt Enable
5
6
Disable
Disabled
0
Enable
Enabled
1
RXEN
RX Enable
1
2
Disable
Disabled
0
Enable
Enabled
1
RXINT
RX Interrupt Enable
3
4
Disable
Disabled
0
Enable
Enabled
1
TXEN
TX Enable
0
1
Disable
Disabled
0
Enable
Enabled
1
TXINT
TX Interrupt Enable
2
3
Disable
Disabled
0
Enable
Enabled
1
TXOVINT
TX Overrun Interrupt Enable
4
5
Disable
Disabled
0
Enable
Enabled
1
DATA
Recieve and Transmit Data Value
0x0
read-write
n
0x0
0x0
INTCLEAR
UART Interrupt CLEAR Register
INTSTATUS
0xC
write-only
n
0x0
0x0
RXINT
RX interrupt
1
2
oneToClear
RXOV
RX Overrun interrupt
3
4
oneToClear
TXINT
TX interrupt
0
1
oneToClear
TXOV
TX Overrun interrupt
2
3
oneToClear
INTSTATUS
UART Interrupt Status Register
0xC
read-only
n
0x0
0x0
RXINT
RX interrupt
1
2
RXOV
RX Overrun interrupt
3
4
TXINT
TX interrupt
0
1
TXOV
TX Overrun interrupt
2
3
STATE
UART Status Register
0x4
read-write
n
0x0
0x0
RXBF
RX Buffer Full
1
2
read-only
RXOV
RX Buffer Overun (write 1 to clear)
3
4
oneToClear
TXBF
TX Buffer Full
0
1
read-only
TXOV
TX Buffer Overun (write 1 to clear)
2
3
oneToClear
UART2
UART 0
UART
0x0
0x0
0x14
registers
n
UART2
UART 2 interrupt
45
BAUDDIV
Baudrate Divider
0x10
read-write
n
0x0
0x0
CTRL
UART Control Register
0x8
read-write
n
0x0
0x0
HSTX
High Speed Test Mode for TX only
6
7
Disable
Disabled
0
Enable
Enabled
1
RVOVINT
RX Overrun Interrupt Enable
5
6
Disable
Disabled
0
Enable
Enabled
1
RXEN
RX Enable
1
2
Disable
Disabled
0
Enable
Enabled
1
RXINT
RX Interrupt Enable
3
4
Disable
Disabled
0
Enable
Enabled
1
TXEN
TX Enable
0
1
Disable
Disabled
0
Enable
Enabled
1
TXINT
TX Interrupt Enable
2
3
Disable
Disabled
0
Enable
Enabled
1
TXOVINT
TX Overrun Interrupt Enable
4
5
Disable
Disabled
0
Enable
Enabled
1
DATA
Recieve and Transmit Data Value
0x0
read-write
n
0x0
0x0
INTCLEAR
UART Interrupt CLEAR Register
INTSTATUS
0xC
write-only
n
0x0
0x0
RXINT
RX interrupt
1
2
oneToClear
RXOV
RX Overrun interrupt
3
4
oneToClear
TXINT
TX interrupt
0
1
oneToClear
TXOV
TX Overrun interrupt
2
3
oneToClear
INTSTATUS
UART Interrupt Status Register
0xC
read-only
n
0x0
0x0
RXINT
RX interrupt
1
2
RXOV
RX Overrun interrupt
3
4
TXINT
TX interrupt
0
1
TXOV
TX Overrun interrupt
2
3
STATE
UART Status Register
0x4
read-write
n
0x0
0x0
RXBF
RX Buffer Full
1
2
read-only
RXOV
RX Buffer Overun (write 1 to clear)
3
4
oneToClear
TXBF
TX Buffer Full
0
1
read-only
TXOV
TX Buffer Overun (write 1 to clear)
2
3
oneToClear
UART3
UART 0
UART
0x0
0x0
0x14
registers
n
UART
UART 3 interrupt
46
BAUDDIV
Baudrate Divider
0x10
read-write
n
0x0
0x0
CTRL
UART Control Register
0x8
read-write
n
0x0
0x0
HSTX
High Speed Test Mode for TX only
6
7
Disable
Disabled
0
Enable
Enabled
1
RVOVINT
RX Overrun Interrupt Enable
5
6
Disable
Disabled
0
Enable
Enabled
1
RXEN
RX Enable
1
2
Disable
Disabled
0
Enable
Enabled
1
RXINT
RX Interrupt Enable
3
4
Disable
Disabled
0
Enable
Enabled
1
TXEN
TX Enable
0
1
Disable
Disabled
0
Enable
Enabled
1
TXINT
TX Interrupt Enable
2
3
Disable
Disabled
0
Enable
Enabled
1
TXOVINT
TX Overrun Interrupt Enable
4
5
Disable
Disabled
0
Enable
Enabled
1
DATA
Recieve and Transmit Data Value
0x0
read-write
n
0x0
0x0
INTCLEAR
UART Interrupt CLEAR Register
INTSTATUS
0xC
write-only
n
0x0
0x0
RXINT
RX interrupt
1
2
oneToClear
RXOV
RX Overrun interrupt
3
4
oneToClear
TXINT
TX interrupt
0
1
oneToClear
TXOV
TX Overrun interrupt
2
3
oneToClear
INTSTATUS
UART Interrupt Status Register
0xC
read-only
n
0x0
0x0
RXINT
RX interrupt
1
2
RXOV
RX Overrun interrupt
3
4
TXINT
TX interrupt
0
1
TXOV
TX Overrun interrupt
2
3
STATE
UART Status Register
0x4
read-write
n
0x0
0x0
RXBF
RX Buffer Full
1
2
read-only
RXOV
RX Buffer Overun (write 1 to clear)
3
4
oneToClear
TXBF
TX Buffer Full
0
1
read-only
TXOV
TX Buffer Overun (write 1 to clear)
2
3
oneToClear
UART4
UART 0
UART
0x0
0x0
0x14
registers
n
UART4
UART 4 interrupt
56
BAUDDIV
Baudrate Divider
0x10
read-write
n
0x0
0x0
CTRL
UART Control Register
0x8
read-write
n
0x0
0x0
HSTX
High Speed Test Mode for TX only
6
7
Disable
Disabled
0
Enable
Enabled
1
RVOVINT
RX Overrun Interrupt Enable
5
6
Disable
Disabled
0
Enable
Enabled
1
RXEN
RX Enable
1
2
Disable
Disabled
0
Enable
Enabled
1
RXINT
RX Interrupt Enable
3
4
Disable
Disabled
0
Enable
Enabled
1
TXEN
TX Enable
0
1
Disable
Disabled
0
Enable
Enabled
1
TXINT
TX Interrupt Enable
2
3
Disable
Disabled
0
Enable
Enabled
1
TXOVINT
TX Overrun Interrupt Enable
4
5
Disable
Disabled
0
Enable
Enabled
1
DATA
Recieve and Transmit Data Value
0x0
read-write
n
0x0
0x0
INTCLEAR
UART Interrupt CLEAR Register
INTSTATUS
0xC
write-only
n
0x0
0x0
RXINT
RX interrupt
1
2
oneToClear
RXOV
RX Overrun interrupt
3
4
oneToClear
TXINT
TX interrupt
0
1
oneToClear
TXOV
TX Overrun interrupt
2
3
oneToClear
INTSTATUS
UART Interrupt Status Register
0xC
read-only
n
0x0
0x0
RXINT
RX interrupt
1
2
RXOV
RX Overrun interrupt
3
4
TXINT
TX interrupt
0
1
TXOV
TX Overrun interrupt
2
3
STATE
UART Status Register
0x4
read-write
n
0x0
0x0
RXBF
RX Buffer Full
1
2
read-only
RXOV
RX Buffer Overun (write 1 to clear)
3
4
oneToClear
TXBF
TX Buffer Full
0
1
read-only
TXOV
TX Buffer Overun (write 1 to clear)
2
3
oneToClear
WATCHDOG
Watchdog Timer
WATCHDOG
0x0
0x0
0xC04
registers
n
CONTROL
Control Register
0x8
read-write
n
0x0
0x0
INTEN
Interrupt event enable
0
1
Disable
Disable Watchdog interrupt
0
Enable
Enable Watchdog interrupt
1
RESEN
Watchdog reset output enable
1
2
Disable
Disable Watchdog reset
0
Enable
ENable Watchdog reset
1
INTCLR
Interrupt Clear Register
0xC
write-only
n
0x0
0x0
INT
Interrupt
0
1
oneToClear
LOAD
Load Register
0x0
read-write
n
0x0
0x0
LOCK
Lock Register
0xC00
read-write
n
0x0
0x0
MIS
Mask Interrupt Status Register
0x14
read-only
n
0x0
0x0
MIS
Masked Watchdog interrupt
0
1
RIS
Raw Interrupt Status Register
0x10
read-only
n
0x0
0x0
RIS
Raw watchdog interrupt
0
1
VALUE
Value Register
0x4
read-only
n
0x0
0x0